1. Field of the Invention
This invention relates generally to semiconductor manufacture and more particularly to structures and methods for forming low resistance, high aspect ratio interconnections.
2. Description of the Background
The increasing densities and continued miniaturization of microelectronic features has lead to the increased usage of high aspect ratio (AR) (defined as the ratio of height to width) features. For example, in very large scale integration (VLSI) high aspect ratio features include contacts, vias, lines, and other apertures. Reliable formation of high aspect ratio features is a key to the continued evolution of VLSI and microelectronic design.
However, contact resistance increases exponentially with technology scaling. Until recently, tungsten (W) has been the metal of choice for filling VLSI features, however the need to reduce contact resistances has lead to the introduction of alternative conductive fillers. Copper (Cu) is being considered as an alternative conductive metal for filling the VLSI features due to its low resistivity, however copper readily diffuses into neighboring layers, such as dielectric layers and silicon. Such Cu diffusion causes current leakage and reliability failure in circuits. Diffusion barriers or liners are introduced to prevent the copper diffusion, to encapsulate the copper interconnect, and to provide improved adhesion to the dielectric layers. For high aspect ratio features, the diffusion barrier should be thin and uniform in order to avoid the introduction of substantial resistance to the interconnection. Preferred diffusion barrier materials are refractory materials such as tantalum, tungsten, tantalum nitride, tungsten nitride, titanium and titanium nitride. However, the additional resistance introduced by the liner/diffusion barrier has the potential to mitigate the advantages of copper over tungsten. In addition, conformality of barrier/liner films and Cu fill integrity degrades significantly with increasing aspect ratios.